1. Field of the Invention
The present invention relates to a bit sequential type parallel comparator, and particularly to an improved bit sequential type parallel comparator capable of locating a minimum value among values of `m` bits stored in `n` registers within `m` clock cycles and the location thereof by bit-sequentially receiving those values.
2. Description of the Conventional Art
Referring to FIG. 1, a conventional bit sequential type parallel comparator includes first through fourth comparators 100 through 103 provided for outputting a least value by comparing data pairs of 8-bit inputted in the form of four data of 8-bit from 8 registers(not shown) `a` through `h`; fifth and sixth comparators 104, 105 provided for each outputting a least value by comparing the 8-bit data outputted from each of the first through fourth comparators 100 through 103 in the form of two pairs of 8 bit data; and a seventh comparator 106 provided for computing a least value by comparing the 8-bit output data by the fifth and sixth comparators 104 and 105.
As described above, in the conventional 8-bit parallel comparator, when the 8-bit data from registers `a` through `h` is parallelly inputted into the first through fourth comparators 100 through 103 in the form of data pairs so as to locate a least value thereamong, the first through fourth comparators 100 through 103 compare the 8-bit data pairs outputted from each of the registers a,b and c,d and e,f and g,h and obtain the four least values thereamong which are in rum compared by the fifth and sixth comparators 10, 105 to obtain the two least values thereamong, which are then compared to obtain the least value therebetween by the seventh comparator 106.
The seventh comparator 106 compares the 8-bit data outputted from the fifth and sixth comparators 104, 105 and obtains a least value thereamong and locates the registers `a` through `h` having the least value.
In addition, referring to FIG. 2, there are provided first through fourth logic circuits 200 through 203 for logically operating upon respective data a3, b3 and a2, b2 and a1, b1 and a0, b0 outputted from two 4-bit registers A and B in the form of data pairs; a fifth logic circuit 204 provided for logically multiplying a result value logically operated by the first through fourth logic circuits 200 through 203 and a control signal outputted in accordance with the size of the two registers A and B; and a sixth logic circuit 205 provided for comparing output values logically operated by the fifth logic circuit 204 and for locating the one of the registers A and B having a least value.
The 4-bit comparator which is the object of a comparison of two registers A and B will now be explained.
To begin with, when the 4-bit data (a3, a2, a1, a0 =1, b3, b2, b1, b0 =1) from respective two registers A and B are inputted, a zero (0) is outputted from each of the first through fourth NOR gates NOR1 through NOR4 of the first through fourth logic circuits 200 through 203 and is inputted respectively into the first through eleventh AND gates AND 1 through AND 11 of the fifth logic circuit 204.
Accordingly, since a zero value is outputted from the first and the third through the eleventh AND gates AND1, AND3 through AND11 and is inputted respectively into a first and second OR gates OR1 and OR2 of a sixth logic circuit 205, the output value of the second AND gate becomes 1, and the output value is inputted into the first OR gate OR1, so that only the first OR gate OR1 outputs 1 irrespective of the input value of the other side, and the second OR gate OR2 outputs zero.
In addition, if the output value of the register B between two registers A and B is larger, only the second OR gate OR2 outputs 1, and the first OR gate OR1 and the eleventh AND gate AND11 output zero through the previously described same process.
In addition, if the value of two registers A and B is same, the output value of the first and second OR gates OR1 and OR2 is zero, and the output value of the eleventh AND gate AND 11 is 1, so that the compared value of 4-bit value of two registers can be obtained.
In addition, referring to FIG. 2, if the value of the register A is larger than that of the register B, a control signal CONT is inputted into a ninth AND gate AND9 as `1`, if the value of the register B is larger than that of the register A, a control signal CONT is inputted into a tenth AND gate AND 10 as `1`, and if the value of both the registers A and B are the same, the control signal CONT is inputted into the eleventh AND gate AND 11 as `1`.
However, since the conventional 4-bit or 8-bit parallel comparator uses a method of computing a least value by comparing the value of M-bit register with the value of the other register, the conventional comparator has disadvantages in that it needs much time so at to compare the output values when a plurality of registers are used. In addition, the conventional 4-bit or 8-bit parallel comparator must employ a plurality of comparators to compute the least values outputted from the many registers.